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Instruction set architectures
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#	Item
531	PA-RISC 2.0 Firmware Architecture Reference Specification Version 1.0 Printed in U.S.A. August 22, 2001 Add to Reading List Source URL: ftp.parisc-linux.org Language: English - Date: 2001-09-04 11:38:08 Instruction set architectures Subroutines Source code Assembly languages Calling convention Pointer Addressing mode 64-bit Reduced instruction set computing Computing Computer programming Software engineering
532	A backend table for the 6500 microprocessor Jan van Dalen ABSTRACT The backend table is part of the Amsterdam Compiler Kit (ACK). It translates the intermediate language family EM to a machine code for the MCS6500 microp Add to Reading List Source URL: tack.sourceforge.net Language: English - Date: 2011-02-11 16:00:22 Instruction set architectures Assembly languages Addressing mode Machine code Stack machine Memory address MOS Technology Zero page Motorola 68000 Computer architecture Computing Computer engineering
533	Migration Specialties International, Inc. 217 West 2nd Street, Florence, CO[removed][removed]E-mail: [removed] www.MigrationSpecialties.com Bruce Claremont, May 2006 Add to Reading List Source URL: www.migrationspecialties.com Language: English - Date: 2015-02-27 19:39:08 Hewlett-Packard Instruction set architectures Compilers Migration RPG VAX RPG II OpenVMS VAX IBM RPG Digital Equipment Corporation Computing Computer architecture Cluster computing
534	Transmeta’s Crusoe: Cool Chips for Mobile Computing David R. Ditzel Chief Executive Officer Transmeta Corporation Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:38:01 Computer engineering Parallel computing Transmeta Instruction set architectures X86 Code morphing Very long instruction word Code Morphing Software Central processing unit Computing Computer architecture Embedded microprocessors
535	MC9S08QG9: Technical Data Sheet for MC9S08QG8/QG4 MCUs Add to Reading List Source URL: www.bairesrobotics.com.ar Language: English - Date: 2015-03-04 09:15:02 Electronic engineering Embedded systems Instruction set architectures Central processing unit I²C Interrupt TI MSP430 Freescale RS08 Computer architecture Microcontrollers Electronics
536	R3081 Mezzanine for VME6U6 Users Manual 15. R3081 Mezzanine The R3081 Mezzanine provides 2 independent MIPS R3081 RISC processors that appear to the host system as two additional resources of the VME6U6. In addition, the Add to Reading List Source URL: www.cacdsp.com Language: English - Date: 1998-02-03 17:01:15 MIPS architecture Central processing unit Coprocessor COFF Booting Digital signal processor Computer architecture MIPS Technologies Instruction set architectures
537	HC17.S2T1 A Milliflow Aggregation Processor.ppt Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:45:43 Computer memory Direct memory access Motherboard Instruction set architectures Microcontrollers 64-bit Embedded microprocessors Blackfin Forwarding plane Computer hardware Computer architecture Computing
538	Danville Signal Processing, Inc Add to Reading List Source URL: www.danvillesignal.com Language: English - Date: 2014-08-22 14:57:03 Microcontrollers Embedded systems Digital signal processors Instruction set architectures Non-volatile memory Joint Test Action Group Flash memory Blackfin USB flash drive Computer hardware Computing Computer architecture
539	V810 FAMILYTM 32-BIT MICROPROCESSOR ARCHITECTURE V805TM Add to Reading List Source URL: www.goliathindustries.com Language: English - Date: 2008-01-27 01:39:25 Assembly languages Instruction set Addressing mode Central processing unit INT Zilog Z80 Intel MCS-51 Computer architecture Interrupts Instruction set architectures
540	Gemini: A Power-efficient Chip Multi-Threaded (CMT) UltraSPARC® Processor Sanjiv Kapil Gemini Architect Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:42:23 Microprocessors UltraSPARC III UltraSPARC II Instruction set architectures UltraSPARC T1 UltraSPARC IV SPARC Multi-core processor DIMM Computer hardware Computer architecture Central processing unit

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